FEA Packaging Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

The Role

This position performs finite element analysis for CScale optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required.

Correlation against measured hardware is expected. Results are used for design sign-off, so assumptions must be documented and defensible.

Responsibilities

Thermal analysis

• Build and maintain thermal models spanning die, package, interface materials, lid, and cold plate, and establish cooling boundary conditions and their validity limits.

• Resolve the temperature field across the photonic IC to the resolution photonic design requires, and define the heat extraction path and interface material selection for high-flux die within the assembly.

Structural analysis

• Predict warpage through the assembly process, and own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.

• Analyze bump and interconnect stress, chip-package interaction, and fatigue life, supporting qualification against JEDEC or equivalent methodology.

Methodology and correlation

• Define modeling standards and document assumptions such that results are auditable.

• Lead correlation against measured temperature, warpage, cross-section, and reliability data, and revise methodology accordingly.

Design and supplier support

• Provide requirements, constraints, and sign-off criteria during architecture definition rather than after design freeze.

• Engage substrate suppliers, OSATs, and cooling and material vendors on process assumptions and measured data.

Required Qualifications

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.

• 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.

• Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain — for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.

• Sound FEA fundamentals: meshing judgment, boundary condition selection, convergence, and the ability to defend a model rather than only to run one.

• Demonstrated correlation of simulation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.

• Experience with advanced packaging construction: flip chip, 2.5D/3D, interposers, and heterogeneous integration.

Preferred Qualifications

• Depth in nonlinear and time-dependent material behavior: creep, viscoplasticity, viscoelasticity, and fatigue.

• Silicon photonics or optoelectronic packaging, including thermo-optic sensitivity or warpage as an optical alignment constraint.

• Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.

• Direct-to-chip liquid cooling, or chip-package interaction and low-k dielectric stress.

• Scripting for model automation and parametric studies, and design of experiments methodology.

Scope and Impact

This position provides the physics basis for package architecture decisions and qualification.