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Principal Senior Engineer - FPGA Design - $30K Sign On Bonus

BAE Systems

Westminster, COFull-time$133–226K/yrSeen 3 days agoSeen in employer's feed 3 days ago

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At a glance

Compensation
$133–226K/yr
Location
Westminster, CO
Schedule
Full-time
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Requirements

Credentials this posting asks for.

Security clearance

Job overview

BAE Systems seeks a Principal Senior Engineer to develop FPGA and digital IP for tactical RF and high-reliability electronic systems. The role spans R&D, proof-of-concept, and production programs, including system-on-chip architectures, test fixtures, and reusable circuits. The position is on-site five days per week in the primary work location. A minimum $30,000 sign-on bonus is offered to external hires.

Skills & qualifications

RequiredNice to have

Skills

FPGA DesignDigital System PartitioningElectronic Circuit DesignElectronic SystemsVHDLVerilogSystemVerilogAMD Vivado/VitisSiemens ModelSim/QuestaSimRequirements FlowdownCommunicationPresentationHigh-Speed Digital ElectronicsEmbedded Processor SystemsOVM/UVM VerificationDigital/FPGA SpecificationsPCIEthernetSignal ProcessingDSP TechniquesCybersecuritySpace or Military Experience

Qualifications

Bachelor's in Engineering or Related Technical Field8+ Years Related ExperienceAccredited Institution DegreeWilling and Eligible for Clearance SubmissionAble to Maintain Applicable Clearance

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k) Match
Paid Time Off
Parental Leave

Full job description

Job Description

Minimum $30,000 Sign On Bonus being offered for external hires.

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical talent and organizational leadership that enables the successful delivery of high-impact discriminating technologies for our customers missions. Our collaborative, cross-functional teams are committed to innovation, integrity, continual learning and strong execution.

What You ll Do:

  • Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems.

  • Work in a fast-paced team environment on a variety of R&D, proof of concept, and production programs.

  • FPGA development and digital IP integration for tactical RF, high reliability electronic systems. Assignments include designs which will include SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols.

  • Design and implement test fixtures including test plans for both chip-level and board level environments and create reusable circuits that can be utilized across multiple projects.

  • Maintain a regular and predictable work schedule.

  • Establish and maintain effective working relationships within the department, the Strategic Business Units, Strategic Capabilities Units and the Company. Interact appropriately with others in order to maintain a positive and productive work environment.

  • Perform other duties as necessary.

On-Site Work Environment: This position requires regular in-person engagement by working on-site five days each normally scheduled week in the primary work location. Travel and local commute between company campuses and other possible non-company locations may be required.

Working Conditions:

  • Work is performed in an office, laboratory, production floor, or cleanroom, outdoors or remote research environment.

  • May occasionally work in production work centers where use of protective equipment and gear is required.

  • May access other facilities in various weather conditions.

Required Education, Experience, & Skills

  • BS degree or higher in Engineering or a related technical field is required plus 8 or more years related experience.

  • Each higher-level degree, i.e., Master s Degree or Ph.D., may substitute for two years of experience. Related technical experience may be considered in lieu of education. Degree must be from a university, college, or school which is accredited by an agency recognized by the US Secretary of Education, US Department of Education.

  • Digital system partitioning and advanced function implementation in FPGAs.

  • Solid electronic circuit design and electronic systems background.

  • Expertise in VHDL/Verilog and System Verilog.

  • Experience with FPGA design tools including AMD Vivado/Vitis and Siemens Modelsim/Questasim.

  • Ability to work requirements and flow down for system/subsystem/box/board needs.

  • Good communication skills as well as excellent presentation skills.

#LI-LB3

A security clearance or access with Polygraph is not required to be eligible for this position. However, the applicant must be willing and eligible for submission, depending on program requirements, after an offer is accepted and must be able to maintain the applicable clearance/access.

Preferred Education, Experience, & Skills

  • Solid design, documentation and implementation of high-speed digital electronics, FPGAs, and embedded processor systems.

  • Experience with OVM/UVM Verification methodologies.

  • Experience developing specifications, cost, schedule, and resource requirements for digital/FPGA designs.

  • Familiarity with high-speed interfaces (PCI, Ethernet).

  • Familiarity with Signal Processing algorithms and DSP techniques.

  • Experience with cybersecurity topics/techniques.

  • Space or military experience.

Pay Information

Full-Time Salary Range: $132962 - $226035

Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.

Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.

Principal Senior Engineer - FPGA Design - $30K Sign On Bonus

131378BR

EEO Career Site Equal Opportunity Employer. Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression

How this job compares

Set against the 11,178 open Systems Engineer jobs on Olive Jobs, counted November 2, 2026.

Pay
  • This posting$133–226K/yr
  • Colorado median$115–177K/yr909 salary ranges
  • US median$116–188K/yr8,191 salary ranges

This range's midpoint, $179K, is 22% above the Colorado median midpoint ($148K) — in the top quarter of Systems Engineer salary ranges in Colorado.

Openings
Olive Jobs lists 1,055 open Systems Engineer jobs in Colorado and 11,178 across the US. 4% of them nationwide are listed as remote or flexible.
Hiring the most in Colorado
Experience
This posting asks for at least 8 years of experience; Systems Engineer postings that state a minimum ask for 5 years at the median (9,433 postings).
Education
4,567 of the 11,178 open Systems Engineer jobs (41%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on November 2, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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