
Senior DFX Engineer, Volume Diagnosis - VLSI
Taipei, Taipei City, TaiwanFull-timePosted 6 days agoStill listed 6 days ago
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Job overview
NVIDIA seeks a senior DFX engineer in Taiwan to lead volume diagnosis and yield‑learning initiatives, improving manufacturability, accelerating root‑cause identification, and guiding corrective actions from bring‑up through volume production and field return analysis.
Skills & qualifications
Skills
Qualifications
Full job description
NVIDIA has been redefining computer graphics, gaming, and accelerated computing through a long history of innovation driven by outstanding technology and talent. As AI reshapes the future of computing, our GPUs are enabling intelligent systems across data center, robotics, automotive, and beyond. Join our VLSI team in Taiwan as an expert DFX specialist and play a key role in advancing silicon quality and production perfection.
In this role, you will lead volume diagnosis and yield-learning strategies. These efforts improve manufacturability, accelerate root-cause identification, and guide corrective actions from bring-up through volume production and field return analysis. You will influence debug methodology, data-driven quality analysis, and coordinate multi-functional execution worldwide. This is an opportunity to work on technology at scale and directly influence how NVIDIA products achieve world-class quality in production.
What you'll be doing
- Implement volume diagnosis using industry-standard diagnostic solutions to process fail logs, localize defects, and generate actionable analysis results.
- Drive yield improvement through data-driven debug, systematic defect Pareto analysis, and rapid feedback loops that convert diagnosis results into corrective actions for manufacturing and product teams.
- Partner with multi-functional teams worldwide across DFX, test engineering, operations, foundry, and failure-analysis participants to accelerate root-cause isolation and production issue resolution.
- Analyze production test and diagnosis data to discover yield limiters and improve test efficiency, silicon quality, and manufacturability.
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What we need to see
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience.
- 5+ years of experience in DFT, DFX, product engineering, silicon debug, yield engineering, or a closely related semiconductor field.
- Strong understanding of volume diagnosis, systematic defect analysis, and yield improvement in volume manufacturing.
- Hands-on experience with commercial diagnosis tools and production diagnosis flows, including fail-log processing, root-cause analysis, and using silicon data to improve yield, quality, and test efficiency.
- Collaboration and interpersonal skills for working across global engineering, operations, and manufacturing teams.
Ways to stand out from the crowd
- Familiarity with physical failure analysis flows at chip foundries, including how software diagnosis guides direct-PFA candidate selection and defect localization.
- Knowledge of ATE, CP, FT, SLT, or board-level test flows and their impact on yield improvement.
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