Thermal Simulation Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

The Role

This position owns thermal modeling for CScale optical engines, from die-level power maps through cooling boundary conditions, and the correlation of those models against measured hardware.

Thermal design here is a functional requirement rather than a reliability margin. Photonic device behavior is temperature-dependent, so wavelength and channel-to-channel uniformity shift with the temperature field across the photonic IC. The assembly also contains a small-footprint, high-flux die whose temperature must be held within a narrow window. The optical engine operates in a thermally shared environment. The deliverable is a defensible temperature field, not a junction temperature.

Responsibilities

Thermal modeling and architecture

• Build and maintain thermal models of the optical engine spanning die, package, interface materials, lid, and cold plate, for air- and liquid-cooled configurations.

• Establish the cooling boundary condition methodology and its validity limits, and quantify thermal crosstalk from adjacent high-power devices.

• Resolve the temperature field across the photonic IC to the resolution photonic design requires, and own the resulting gradient and uniformity specifications.

Materials and interfaces

• Define the heat extraction path for high-flux die within the assembly, die attach, and thermal interface material selection where footprint and power density are constraining.

• Quantify the sensitivity of engine temperature to material property tolerance and assembly variation.

Correlation and design influence

• Define the thermal characterization plan and lead simulation-to-hardware correlation to a stated and tracked accuracy tolerance.

• Provide thermal requirements and constraints to package layout, photonic design, and electrical design during architecture definition rather than after freeze.

• Generate reduced-order thermal models for system integrators and customers, and engage cold plate, heat sink, and thermal material suppliers.

Required Qualifications

• MS or PhD in Mechanical Engineering, Electrical Engineering, Physics, or equivalent practical background.

• 6+ years of thermal simulation for semiconductor packages or electronic systems, including one product carried from architecture through hardware correlation.

• Expert proficiency in a commercial thermal or CFD tool for electronics: Ansys Icepak or Fluent, Simcenter Flotherm, Cadence Celsius, or equivalent.

• Command of heat transfer fundamentals sufficient to defend a model rather than only to run one.

• Demonstrated correlation of thermal simulation against measured hardware, with methodology revised on that basis.

Preferred Qualifications

• Silicon photonics or optoelectronic thermal work, particularly thermo-optic sensitivity and wavelength stability.

• Thermal design for small-footprint, high-flux die.

• Direct-to-chip liquid cooling and cold plate design or specification.

• 2.5D/3D package thermal modeling, and coupled electrothermal or thermal-structural workflows.

• First-generation product experience where the thermal methodology had to be established rather than inherited.