Quantum PDK Engineer

About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction The Quantum PDK Design Enablement (MTS) role is a technical contributor within the Quantum Technology Solutions organization focused on enabling scalable quantum computing platforms. This position supports development of Process Design Kits (PDKs), compact models, and design enablement infrastructure that bridge advanced quantum device physics with semiconductor manufacturing and circuit design, including cryogenic control and readout ICs. This role operates at the intersection of device physics, modeling, and EDA, translating emerging quantum device technologies into usable, manufacturable, and customer-ready design environments. Summary of Role As a Member of Technical Staff, this role contributes to the development, deployment, and support of PDKs for quantum device platforms and associated cryogenic electronics. The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes hands-on technical execution, automation, and strong cross-functional collaboration across device engineering, process integration, modeling, and design teams to enable scalable and high-performance quantum systems. Essential Responsibilities Develop, deploy, and maintain PDKs (tech files, model files, rule decks, runtime code) for quantum devices and cryogenic control/readout ICs Create device libraries and parameterized cells (PCells), translating process design rules and SPICE/model specifications into design-ready implementations Support compact model development, parameter extraction, and correlation across TCAD, silicon data, and cryogenic characterization Integrate and validate PDKs within EDA environments (e.g., LVS/DRC, simulation flows), including development of automation tools representing fab processes Design test structures and test chips, and develop validation plans to ensure model accuracy and silicon correlation Develop and execute QA workflows, including DRC/LVS test cases and release validation, to ensure high-quality customer deliveries Analyze device and circuit data to identify variability, reliability risks, and performance trends; support yield-learning and root-cause analysis Create and maintain PDK documentation (release notes, application notes, known issues) and communicate usage guidance to users Collaborate cross-functionally with device, process, integration, and EDA teams to align design enablement with technology capabilities Contribute innovative ideas that may lead to intellectual property, patents, or advanced design enablement methodologies Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. Required Qualifications BS (MS preferred) in Electrical Engineering, Microelectronics, Physics, Computer Science, or related field ~5-6+ years of experience in semiconductor design enablement, PDK development, or EDA Strong knowledge of semiconductor device physics and electronic devices Experience with EDA tools (e.g., Cadence Virtuoso or similar) and design flows Experience with device modeling, test structures, or silicon validation Familiarity with scripting (e.g., Python, Tcl, Perl) and Unix/Linux environments Strong analytical, debugging, and problem-solving skills Effective communication and teamwork skills; detail-oriented and self-motivated Preferred Qualifications Experience with Cadence SKILL, PC ll d