
Senior RTL Design
Remote · USJob$200–500K/yrSeen todaySeen in employer's feed today
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Job overview
The Senior RTL Design Engineer will design, implement, and optimize RTL for key portions of the Velaura SoC. The role collaborates with architects, software teams, verification, and physical design to develop microarchitectures, define hardware interfaces and performance-critical interactions, and improve design performance, power, area, scalability, and reliability. The position also contributes to performance analysis, design reviews, and engineering workflows.
Skills & qualifications
Skills
Benefits
Full job description
Job Title: Senior RTL Design EngineerJob Description
We are seeking a highly skilled Senior RTL Design Engineer to join our team. You will play a pivotal role in designing, implementing, and optimizing RTL for key portions of the Velaura SoC. Your work will involve collaborating closely with architects, software teams, and cross-disciplinary engineering teams to ensure the development of robust and efficient microarchitectures.
Responsibilities
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Design, implement, and optimize RTL for key portions of the Velaura SoC.
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Collaborate with architects to develop robust and efficient microarchitectures.
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Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
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Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
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Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
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Optimize designs for performance, power, area, scalability, and reliability.
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Partner closely with verification and physical design teams throughout the development cycle.
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Analyze performance bottlenecks and propose architectural and implementation improvements.
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Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
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Participate in design reviews and contribute to a culture of technical excellence.
Essential Skills
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Experience designing RTL for complex digital systems.
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Strong understanding of computer architecture, microarchitecture, and digital design.
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Experience with Verilog/SystemVerilog and modern RTL design methodologies.
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Familiarity with performance, power, and area tradeoffs.
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Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
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Experience with hardware/software co-design and system-level performance optimization.
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Strong debugging and problem-solving skills.
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Ability to work effectively in a collaborative, multidisciplinary engineering environment.
Additional Skills & Qualifications
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Experience with AI, machine learning, or edge AI hardware.
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Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
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Knowledge of low-power design techniques and power management architectures.
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Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
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Experience using modern AI tools and workflows to accelerate engineering productivity.
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Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS), aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.
Work Environment
You will work in a dynamic and collaborative engineering environment, utilizing cutting-edge engineering tools and workflows. The role involves cross-disciplinary collaboration to ensure the development of state-of-the-art technology.
Job Type & Location
This is a Permanent position based out of Santa Clara, CA.
Pay and Benefits
The pay range for this position is $200000.00 - $500000.00/yr.
Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this role may include the following: Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan Pre-tax and Roth post-tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long-term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave)
Job Type & Location
This is a Permanent position based out of Santa Clara, CA.
Application Deadline
This position is anticipated to close on Nov 4, 2026.
Workplace Type
This is a fully remote position.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options.
San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.
How this job compares
Set against the 2,961 open Hardware Engineer jobs on Olive Jobs, counted October 29, 2026.
- Pay
- This posting$200–500K/yr
- California median$146–214K/yr909 salary ranges
- US median$131–201K/yr2,162 salary ranges
This range's midpoint, $350K, is 97% above the California median midpoint ($178K) — in the top quarter of Hardware Engineer salary ranges in California.
- Openings
- Olive Jobs lists 1,205 open Hardware Engineer jobs in California and 2,961 across the US. Under 1% of them nationwide are listed as remote or flexible.
- Experience
- Hardware Engineer postings that state a minimum ask for 5 years of experience at the median; the middle half ask for 3 to 8 years (2,485 postings).
- Education
- 1,858 of the 2,961 open Hardware Engineer jobs (63%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on October 29, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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