
Principal Product Engineer
Austin, TXFull-timeSeen 2w agoSeen in employer's feed 1 day ago
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Job overview
The role is a Principal Product Engineer in Cadence's Digital and Signoff Group, responsible for providing technical place and route expertise, supporting products, debugging customer issues, running benchmarks, and developing flows for advanced chip design platforms.
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Full job description
AUSTIN
Full time
R56406
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.
You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.You are an excellent communicator.
Position Responsibilities:Support Cadence products in the Digital and Signoff team.Track and debug customer issues and work with R&D and release team on issue resolution.Run design benchmarks and develop flows and solutions.
Position Requirements:MS in EE with 5+ years of experience in Digital Implementation, either as a design engineer or as a product engineer
Or BS in EE with 8+ years of experience in Digital Implementation, either as a design engineer or as a product engineerStrong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including RTL synthesis, placement optimization, clock tree synthesis, routing optimization and silicon signoff.Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.Exposure to, and solid understanding of, hierarchical design methodologies and low power designEnergetic team player with a passion for problem solvingStrong analysis skills with a track record to prove itStrong communication skills (verbal and written)Automation skills using Perl, Tcl and shell scripting
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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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