
Design Verification Architect / Director
Austin, TXFull-time$186–345K/yrSeen 3w agoSeen in employer's feed 1 day ago
Most applications go out cold — see where you stand first. No sign-up to start.
Watch jobs like this. New roles like this one near Austin, TX, by email.
Don't just apply. Show up ready.
Olive works from this exact posting.
At a glance
Olive lists jobs from US employers, including remote roles you can work from the United States.
Requirements
Credentials this posting asks for.
Job overview
At Cadence, the Design Verification Architect / Director leads the Processor Verification team, crafting verification plans, implementing testbenches, and managing coverage while collaborating with cross‑functional groups to guide a team of engineers in verifying complex CPU designs.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
SAN JOSE
AUSTIN
Full time
R56318
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Location
San Jose, CA and Austin, TX
Job Description
Responsibilities
As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals
Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred
Crafting verification plans and executing them to verify highly complex CPU designs.
You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
You will be responsible for coverage collection and closure
You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope
Tracking and reporting the work of 7-10 engineers
Required Skills and Experience:
17+ years of design verification experience
BS (or higher) in EE/Computer Engineering
Proven experience at leading/managing team.
Strong managerial, leadership and interpersonal skills
Excellent knowledge of computer architecture and design verification fundamentals
Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
Exposure to scripting languages like Perl, Unix shell or similar languages
Experience with assembly language programming required
Experience with Formal Verification will be a plus
Experience with the development of fully automated flows
Experience with Gate Level Simulations
Excellent written and oral communication skills necessary
Knowledge of processor verification required
The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
- Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf)
We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected].
Privacy Policy:
Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) .
E-Verify Cadence participates in the
E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Similar jobs, posted recently
Open roles like this one, listed in the last 30 days.
PCIe Design Verification Intern - Summer 2027NVIDIA · Austin, TX · $20–71/hrPosted 4 days agoPosted 4 days ago
Senior ASIC Design Verification Engineer - LPUNVIDIA · Santa Clara, CA (Hybrid) · $168–311K/yrPosted 2w agoPosted 2w ago
Pre-Silicon Verification EngineerIntel · Hillsboro, OR (Hybrid) · $122–173K/yrPosted 1 day agoPosted 1 day ago
Custom SOC IP Verification EngineerNVIDIA · Santa Clara, CA · $168–311K/yrPosted 3w agoPosted 3w ago
• AI/ML CAD Engineer, RTL & Design VerificationIntel · Austin, TX (Hybrid) · $122–232K/yrPosted 1w agoPosted 1w ago
You've read the whole posting — now see how you match it.