Display Engineering Intern

Summary:

Reality Labs is building products that make it easier for people to connect with the ones they love most. As a Display Array Modeling Engineering Intern, you will help build pre-silicon simulation models for high pixel-density display arrays to predict front-of-screen artifacts such as crosstalk and mura, and other performance metrics. You will collaborate with cross-functional teams such as panel design and optical engineering.This is a 12 week internship.

Required Skills:

Display Engineering Intern Responsibilities:

1. Design semiconductor circuits using Cadence Virtuoso Schematic Editor and simulate them using Cadence simulation tools (Spectre/SPICE)

2. Build and validate large-array simulation models using combined distributed and lumped loads, incorporating peripheral circuit blocks and improved test bench setups

3. Analyze circuit layouts and incorporate parasitic extraction results into array-level models to predict coupling to sensitive nodes (e.g., anode, drive transistor gate)

4. Correlate simulated predictions (crosstalk, mura, settling behavior, power/load effects) against measured display data to improve model accuracy

5. Operate optical lab instruments (e.g., microscope, spectrometer, imaging colorimeter, probe station) to measure display KPIs such as crosstalk and mura

6. Develop quantifiable, measurable metrics for display artifacts and automate measurement and data analysis using Python/MATLAB

Minimum Qualifications:

Minimum Qualifications:

1. Currently has, or is in the process of obtaining, an MS in Electrical Engineering, Microelectronics, VLSI, or a related field

2. Experience in mixed-signal circuit design, including analog/digital fundamentals, signals and systems, and semiconductor device behavior

3. Hands-on experience with Cadence Virtuoso tools (Schematic Editor) and Cadence circuit simulation (Spectre/SPICE)

4. Understanding of circuit layouts, parasitic effects, and large-array modeling concepts

5. Experience with programming in Python and/or MATLAB for data collection and analysis

6. Must obtain work authorization in the country of employment at the time of hire, and maintain ongoing work authorization during employment

7. Intent to return to full-time degree program after completion of the internship

Preferred Qualifications:

Preferred Qualifications:

1. Currently has, or is in the process of obtaining, a PhD in Electrical Engineering, Microelectronics, VLSI, or a related field

2. Strong preference for background in memory design and characterization, or related array structures (e.g., SRAM, image sensors, solar cell arrays)

3. Familiarity with display technologies (LCD, OLED, uOLED) and display pixel circuits (e.g., multi-transistor pixel architectures)

4. Experience with optical lab instruments such as microscopes, spectrometers, imaging colorimeters, and probe stations

5. Experience developing quantitative optical/visual performance metrics (e.g., crosstalk, mura) for displays

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].