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Digital Verification Engineer Lead (MTD, Tualatin, OR)

Teradyne

Tualatin, ORJob$155–248K/yrSeen 2mo agoSeen in employer's feed 6 days ago

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At a glance

Compensation
$155–248K/yr
Location
Tualatin, OR
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Teradyne is hiring a Digital Verification Engineer Lead (MTD, Tualatin, OR). Teradyne is seeking a Digital Verification Engineer Lead to drive FPGA verification projects. This role involves technical leadership for cross-site verification teams and interfacing with hardware, software, and applications groups. The ideal candidate will have a passion for customer success and a determination to excel in a high-performance work environment.

Key focus areas include Act as a digital functional verification technical lead, Plan challenging FPGA verification projects, and Strategize challenging FPGA verification projects.

Successful candidates bring Master's Degree In Electrical Engineering/Computer Engineering/Computer Science Or Equivalent, 10+ Years Relevant Work Experience, and 12+ Years Relevant Work Experience. Important skills include Verification Planning, Testbench Architecture, Functional Verification Cycle, Design Specification Review, Verification Closure, and System Verilog Constraint Random Testing. Preferred (not required): FPGA Design Implementation With System Verilog, Verification Of Automated Test Equipment Functionality, Static Formal Verification, and Dynamic Formal Verification.

Skills & qualifications

RequiredNice to have

Skills

Verification PlanningTestbench ArchitectureFunctional Verification CycleDesign Specification ReviewVerification ClosureSystem Verilog Constraint Random TestingAssertionsFunctional CoverageUVM Testbench DevelopmentVerification IP IntegrationReference Models DevelopmentReference Models IntegrationEthernetPCIeAXIMIPIDRAMFLASHRegression Failures AnalysisVerification Progress TrackingMakefilesShell ProgrammingTCLPerlPythonClearcaseGitSVNIssue TrackingDetail OrientedPlanning SkillsOrganizational SkillsLeading Verification TeamMentoring Junior EngineersFPGA Design Implementation With System VerilogVerification of Automated Test Equipment FunctionalityStatic Formal VerificationDynamic Formal VerificationGVP Source Control Continuous Integration Tool

Qualifications

Master's Degree in Electrical Engineering/Computer Engineering/Computer Science or Equivalent10+ Years Relevant Work Experience12+ Years Relevant Work ExperienceExperience Working With Cross-Site Teams

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
Paid Time Off
Tuition Assistance

Full job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne (http://www.teradyne.com/) companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. hardware, software, applications).

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 12 years of relevant work experience

  • Experience with verification planning and testbench architecture

  • Experience with complete functional verification cycle from Design Specification Review to verification closure

  • Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification

  • Expertise with UVM testbench development and Verification IP integration

  • Experience with Reference models development and integration

  • Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, AXI, MIPI, DRAM, FLASH

  • Experience with regression failures analysis

  • Experience with verification progress tracking

  • Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)

  • Experience working with revision source control (e.g. clearcase, git, svn)

  • Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills.

  • Experience leading verification team

  • Experience working with teams located in different time zones

  • Experience mentoring junior engineers

Desired (but not required) skills/experience:

  • Experience in FPGA design implementation with System Verilog

  • Experience in verification of Automated Test Equipment functionality

  • Static and/or dynamic Formal Verification

  • Experience with GVP source control continuous integration tool

Compensation:

The base salary range for this role is $154,900 - $247,800 . This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here (https://www.teradyne.com/2026-benefit-information-for-us-employees/) to see details

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Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at [email protected] for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.

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