Principal Engineer, AI & ML Design Verification (AI2517) San Jose, California
San Jose, CAFull-time$204–316K/yrPosted 2mo agoStill listed 2w ago
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Job overview
SiMa.ai is hiring a Principal Engineer, AI & ML Design Verification (AI2517) San Jose, California. SiMa.ai seeks a Principal Engineer to lead AI and ML design verification in San Jose, requiring full‑time on‑site work. The role involves independent verification execution, test‑bench development, code‑coverage reviews, debugging, and collaboration with architecture, hardware and software teams, while supporting silicon bring‑up and emulation efforts.
Key focus areas include Independently perform MLA verification execution and closure, Participate in MLA architecture, micro‑architecture and feature discussions and reviews, and Define and develop MLA test bench components using UVM & System Verilog.
Successful candidates bring BS/MS In EE Or CS and 12+ Years Of Experience In Functional Verification. Important skills include UVM, System Verilog, and AMBA Protocols. Preferred (not required): Debug Tools, Coverage Tools, Silicon Debug, and Coding.
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Description
Job Title: Principal Engineer, AI & ML Design Verification Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2517 Description: The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC. As well involved in bring-up and debugging on emulators and silicon. In addition, this job role requires development, enhancement and on-going support and maintenance of MLA Test Bench and Test Cases for SiMa ML IP. Job Description As the experienced MLA Design Verification Engineer, you will
- Independently perform MLA verification execution and closure.
- Participate in MLA architecture, micro-architecture and feature discussions and reviews.
- Define and develop MLA test bench components using UVM & System Verilog.
- Develop and execute a test plans.
- Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
- Manage debugging of test and regression failures.
- Help emulation team with triaging failures.
- Work closely with the Architecture, SoC Hardware and Software teams. Required Background:
- BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
- Very good experience of UVM and System Verilog based verification methodology is a must.
- Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know how of debug & coverage tools.
- Skill set for silicon debug on the lab/board set-up is a plus.
- Good debug, coding and problem solving skills.
- Knowledge of AMBA protocols is a must.
- Formal/SVA knowledge is a plus. Personal attributes: Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills. The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future. In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation. EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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