Etched logo

Physical Design Engineer

Etched

San Jose, CAFull-time$150–275K/yrPosted 1y agoStill listed 4 days ago

Evaluate my fit

Most applications go out cold — see where you stand first. No sign-up to start.

Watch jobs like this.

Don't just apply. Show up ready.

Olive works from this exact posting.

At a glance

Compensation
$150–275K/yr
Location
San Jose, CA
Schedule
Full-time
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

Etched is hiring a Physical Design Engineer. Etched is seeking a Physical Design Engineer to lead block‑level implementation and verification for advanced ASICs. The role involves driving timing closure, optimizing PPA, supervising third‑party design work, and enhancing design flows. Candidates will collaborate with RTL designers, manage dashboards, and work closely with EDA vendors to integrate new features, all within a fully in‑person San Jose team.

Key focus areas include Understand physical design concepts deeply, Run and automate PD flows to close blocks and support ASIC infrastructure, and Collaborate with RTL designers to provide feedback and improve PPA.

Successful candidates bring 5-10+ Years Previous Experience With PD. Important skills include Physical Design, PD Flows, ASIC Infrastructure, CAD Infrastructure, PPA Optimization, and Optimize Tool Flows. Preferred (not required): Modern ML Architectures, LLM Model Architectures, Python, and Scripting Language.

Skills & qualifications

RequiredNice to have

Skills

Physical DesignPD FlowsASIC InfrastructureCAD InfrastructurePPA OptimizationOptimize Tool FlowsBack-End DesignTiming ClosureAdvanced Process NodesCadence InnovusCadence GenusSynopsys ICC2Synopsys Fusion CompilerRTL-to-GDSII FlowsPrimeTimeTempusVoltusUPF-Based Low Power Design MethodologyPower VerificationSynthesisScan InsertionATPGFormal VerificationFloorplanningPlacementCTSRoutingIR DropEM/Antenna AnalysisCreativityFirst Principles ThinkingModern ML ArchitecturesLLM Model ArchitecturesPythonScripting LanguageAI Tools for Programming/CodingStartup ExperienceWorking in Fast-Paced EnvironmentsDrive DashboardsBlock Level ClosureScan Insertion/ATPGModern ML Model Architectures

Qualifications

5-10+ Years Previous Experience With PDTools, Flow, and Design Methodology From RTL Synthesis to GDSII Sign-OffExperience With Advanced Process Nodes (5nm and Below)

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
Relocation Assistance

Full job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities

  • Deeply understand what is involved in physical design

  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure

  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA

  • Drive dashboards that show the convergence of projects related to PD

  • Optimize tool flows, working with EDA vendors to incorporate the latest features

  • Accountable for block level closure

  • Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

  • 5-10+ years of previous experience with PD

  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

  • Experience with back-end design and timing closure on advanced process nodes (5nm and below)

  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows

  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis

  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • Ability to program with Python or another scripting language

  • Familiarity with AI tools for programming/coding

  • Startup experience or comfort working in fast-paced environments

Benefits

  • Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2k per month for those living within walking distance of the office

  • Relocation support for those moving to San Jose (Santana Row)

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different:

Etched believes in the Bitter Lesson . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Similar jobs, posted recently

Open roles like this one, listed in the last 30 days.

You've read the whole posting — now see how you match it.

Evaluate my fit