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ASIC Senior Verification Engineer

Retym, Inc

Austin, TXFull-timeNo compensation foundPosted 1mo agoVerified open 3 days ago
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At a glance

Compensation
No compensation found
Location
Austin, TX
Schedule
Full-time
Work Authorization
Not specified

Job overview

Retym, Inc is hiring an ASIC Senior Verification Engineer. Retym, Inc. is seeking a Senior Verification Engineer to drive complex RTL design verification activities for next-generation high-speed communication technology. The role involves owning block/cluster verification from scratch, leading test bench architecture and functional coverage, and collaborating with design, architecture, and algorithm teams. The engineer will also mentor less experienced team members.

Key focus areas include Own block/cluster verification end to end from scratch, Lead efforts of test bench architecture, Vplan definition and functional coverage, and Work closely with the design, architecture, algo teams and other stakeholders.

Successful candidates bring 10+ Years Experience and 2+ Full Block/System Verification Cycles. Important skills include RTL Design Verification, Test Bench Architecture, Vplan Definition, Functional Coverage, VLSI Verification Flow, and VLSI Verification Languages.

Skills & qualifications

RequiredNice to have

Skills

RTL Design VerificationTest Bench ArchitectureVplan DefinitionFunctional CoverageVLSI Verification FlowVLSI Verification LanguagesVLSI Verification ConceptseRMUVMVerilogCoverage CollectionData PathData ProtocolsEthernet

Qualifications

10+ Years of Experience2+ Full Block/System Verification Cycles

Full job description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.

Requirements:

Key responsibilities:

  • Ownership of block\cluster verification end to end from scratch.
  • Lead efforts of test bench architecture, Vplan definition and functional coverage.
  • Work closely with the design, architecture, algo teams and other stakeholders.
  • Support other team members and mentor less experienced engineers.

Requirements

  • 10+ years of experience – a must
  • Performed at last 2 or more full block/system verification cycles.
  • In depth knowledge in VLSI verification flow, languages and concepts.
  • Experience in data path or data protocols, specifically Ethernet - preferred
  • Verification using one of the known methodologies (eRM, UVM).

Responsibilities

  • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
  • Build verification environments using SystemVerilog and UVM.
  • Identify and write all types of coverage measures for corner-cases.
  • Debug the functionality with design engineers.
  • Perform coverage collection and follow the metrices to close the full functionality.

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