Member of Technical Staff, Hardware, Physical Design Engineer
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At a glance
Requirements
Credentials this posting asks for.
Job overview
River AI is hiring a Member of Technical Staff, Hardware, Physical Design Engineer. River AI seeks exceptional physical design engineers to transform high‑performance architectural concepts into production‑ready silicon, owning the implementation flow from synthesis through tape‑out and collaborating closely with RTL designers to close timing, electrical, and verification challenges.
Key focus areas include Drive synthesis and place‑and‑route from RTL through placement, CTS, and routing, Maximize PPA by optimizing layout density and power delivery networks, and Close timing and electrical issues through static timing analysis and signal integrity fixes.
Important skills include Physical Design, Static Timing Analysis, Signal Integrity, Electromigration, Tcl (Programming Language), and Debugging. Preferred (not required): Optimizing Physical Layouts For Highly Parallel Compute Structures, Systolic Arrays, Large Tensor Execution Units, and High-Bandwidth Memory Interfaces.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
At River, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
Who we are We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
About the Role We are looking for exceptional physical design engineers to transform our high-performance architectural concepts into production-ready silicon. You will own the physical implementation flow from synthesis through tape-out, pushing the absolute limits of advanced foundry nodes to maximize PPA. You will take ownership of block-level and top-level physical design, collaborating tightly with RTL designers to close timing, electrical, and physical verification for our custom AI accelerator.
What You’ll Do
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Drive Synthesis and Place-and-Route: Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks.
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Maximize PPA: Optimize layout topologies to maximize cell density and utilization, architecting robust power delivery networks (PDN) to minimize IR drop and meet aggressive frequency targets on advanced foundry nodes.
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Close Timing & Electricals: Conduct static timing analysis (STA), fix setup/hold violations across complex clock domains, and resolve signal integrity (SI), electromigration (EM) and IR-drop constraints.
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Execute Physical Verification: Run and debug sign-off physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna rule compliance.
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Co-Design with RTL: Partner directly with the RTL team to provide early physical feedback on logic structures, pipeline depth, and routing congestion to streamline implementation closure.
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Advance Flow Automation: Integrate and develop next-generation AI-driven EDA tools and workflows to fundamentally accelerate the physical implementation cycle and optimize design closure. Skills and Qualifications Minimum Qualifications:
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Bachelor’s degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
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Deep hands-on proficiency with industry-standard physical design, timing, and sign-off tools (e.g., Innovus, Fusion Compiler, PrimeTime, RedHawk).
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Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF).
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Exceptional debugging skills with a first-principles approach to navigating complex trade-offs between congestion, timing slack, and power density in highly utilized designs.
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A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with RTL and architecture teams. Preferred Qualifications: (We encourage you to apply even if you don't meet all of these)
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An extensive track record of delivering high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple successful production tape-outs.
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Hands-on experience optimizing physical layouts for highly parallel compute structures, such as systolic arrays, large tensor execution units, or high-bandwidth memory (HBM) interfaces.
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Experience custom-scripting or extending EDA tools (using Tcl, Python, or specialized ML APIs) to automate physical design closure and build bespoke workflow pipelines. Logistics
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Location: This role is based in Austin, Texas or Palo Alto, California.
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Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
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Visa Sponsorship: We sponsor visas and are committed to supporting the process for the right candidate.
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Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
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