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Senior Mixed-Signal IC Design Engineer – DLL, Delay Line & Clocking Architectures

Insight Global

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At a glance

Compensation
No compensation found
Location
Redmond, WA
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Design and develop Delay Locked Loops (DLLs) for high-performance clock generation, synchronization, and phase alignment, and optimize programmable delay lines and clock distribution solutions.

Skills & qualifications

RequiredNice to have

Skills

Delay Locked LoopsDelay LinesPhase Alignment CircuitsClock Conditioning CircuitsClock Tree DesignClock Deskew TechniquesPhase Detection CircuitsTiming Recovery SystemsJitter AnalysisPhase NoiseTiming UncertaintySkew OptimizationLoop StabilityTransistor-Level DesignAdvanced CMOS TechnologiesCadence VirtuosoSimulation Tools

Qualifications

Bachelor's in Electrical Engineering5+ Years Experience in Analog or Mixed-Signal Ic Design

Full job description

Job Description

Design and develop Delay Locked Loops (DLLs) for high-performance clock generation, synchronization, and phase alignment. Architect and optimize programmable delay lines and delay blocks for precise timing control. Develop clock distribution solutions including: Clock trees Clock buffers Clock dividers Clock deskew circuits Duty-cycle correction circuits Design and analyze DLL phase detectors, phase interpolators, charge pumps, and loop control circuitry. Perform extensive jitter analysis, including: Random jitter Deterministic jitter Supply-induced jitter Clock uncertainty Phase noise contributions Optimize clocking architectures for low skew, low power, and high timing accuracy. Analyze delay-line performance across PVT corners and process variations. Develop timing closure strategies with digital implementation and physical design teams. Support clock architecture development for high-speed mixed-signal and data converter systems. Collaborate with layout engineers to minimize clock path mismatch and parasitic effects. Validate silicon performance through lab characterization and clock integrity measurements.

Skills and Requirements

BS, MS, or PhD in Electrical Engineering. 5+ years of experience in analog or mixed-signal IC design. Strong experience designing: DLLs (Delay Locked Loops) Delay lines Phase alignment circuits Clock conditioning circuits Deep understanding of clock generation and distribution architectures. Experience with: Clock tree design Clock deskew techniques Phase detection circuits Timing recovery systems Strong knowledge of: Jitter analysis Phase noise Timing uncertainty Skew optimization Loop stability Experience with transistor-level design in advanced CMOS technologies. Proficiency with Cadence Virtuoso and industry-standard simulation tools.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].

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