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Staff Engineer, Hardware Design (AI2540) San Jose, California

SiMa.ai

San Jose, CAFull-time$137–219K/yrPosted 3 days agoStill listed 2 days ago

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At a glance

Compensation
$137–219K/yr
Location
San Jose, CA
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Master's degree

Job overview

SiMa.ai seeks a Staff ASIC Design Engineer to own microarchitecture definition, RTL implementation, and block-level silicon development, collaborating across verification, physical design, architecture, and firmware teams in a fast‑paced startup environment.

Skills & qualifications

RequiredNice to have

Skills

VerilogMicroarchitectureCollaborationMachine LearningProblem SolvingVerilog/SystemVerilogRTL DesignSynthesisTiming ClosureDFTMachine Learning HardwareSoC IntegrationFirmware DevelopmentDriver Development

Qualifications

Master's Degree in Electrical Engineering or Related Field5+ Years ASIC Design Experience

Full job description

Description

Job Title: Staff Engineer, Hardware Design Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2540 Job Description: We are seeking a Staff​ ASIC Design Engineer with deep expertise in RTL design and ground-up block-level silicon development. The ideal candidate will own complex design blocks from microarchitecture and RTL implementation through verification support and silicon bring-up. This position offers the opportunity to shape and influence the design architecture and methodology of SiMa's silicon in a fast-paced startup environment. Areas of Focus:

  • Own microarchitecture definition and RTL implementation of complex blocks from concept through silicon.
  • Drive ground-up block design, owning each block from specification and microarchitecture to RTL, integration, and bring-up.
  • Develop high-quality, synthesizable RTL (Verilog/SystemVerilog), including custom logic, protocol adaptation, and data-path optimizations.
  • Define block-level interfaces, microarchitectural trade-offs, and design specifications.
  • Collaborate with verification, physical design, architecture, and firmware teams to ensure each block meets functional, timing, power, and area targets.
  • Drive block-level synthesis, timing closure, and DFT readiness.

Key Requirements:

  • Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC design, with a strong focus on block-level RTL design and silicon development.
  • Proven track record of ground-up block design, taking blocks from microarchitecture and RTL through to working silicon.
  • Expert-level RTL design skills (Verilog/SystemVerilog), with hands-on experience in synthesis, timing closure, and DFT concepts.
  • Strong understanding of microarchitecture trade-offs, data-path and control logic design, and block-level optimization for power, performance, and area.

Nice to Have:

  • Experience designing hardware for machine learning / AI accelerators.
  • Experience designing hardware for complex algorithms
  • Experience integrating blocks into larger SoCs.
  • Exposure to firmware or driver development

Personal attributes: Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills. The annual salary for this position ranges from $136,900 - $219,000. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future. In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation. EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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