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Leader, ASIC Engineering

Cisco

Hsinchu, Hsinchu City, Taiwan · HybridFull-timePosted 2 days agoStill listed 1 day ago

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At a glance

Compensation
No compensation found
Location
Hsinchu, Hsinchu City, TaiwanHybrid
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Lead semiconductor test and product development engineering and operational readiness for Cisco Silicon One high‑performance networking ASICs across wafer sort and final test, driving test architecture, OSAT management, silicon bring‑up, yield and reliability, and team leadership.

Skills & qualifications

RequiredNice to have

Skills

Advantest V93000SmarTest 7SmarTest 8Automated Test EquipmentDigital TestingHigh‑Speed SerDes TestingDFT/DFM ArchitecturesScan/ATPGMBISTBoundary ScanHigh‑Speed I/O TestingOSAT Production WorkflowsFailure AnalysisYield OptimizationReliability Stress QualificationHTOLESDLUThermal CharacterizationTeam LeadershipResource Allocation

Qualifications

Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering or Related Field10+ Years of Hands‑on Semiconductor ATE Test Development Experience With Complex SoC/ASICs3+ Years in Technical Leadership or Engineering ManagementDeep Knowledge of Silicon Bring‑Up DFT/DFM Architectures and OSAT Production Workflows

Full job description

Role Summary: Lead semiconductor test and product development engineering and operational readiness for Cisco Silicon One high-performance networking ASICs across wafer sort and final test.

Key Responsibilities:

  • Test Architecture & Development: Drive test program development and verification on automated test equipment (Advantest V93000 / SmarTest 7 & SmarTest 8) across digital, high-speed SerDes, and other IP blocks.
  • OSAT Management & Execution: Partner closely with OSAT manufacturing suppliers for tester capacity, load boards/probe cards readiness, yield optimization, and test time reduction (TTR).
  • Silicon Milestones & Bring-up: Lead test readiness and execution across product qualification gates from pre-silicon tape-out through first silicon bring-up, characterization, qualification and to mass production.
  • Yield & Reliability: Drive failure analysis, wafer sort/FT yield pareto tracking, yield to target, and reliability stress qualification (HTOL, ESD, LU, thermal characterization).
  • Team Leadership: Manage, mentor, and guide test and product engineers, resource allocation to hit program milestones.

Qualifications:

  • Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of hands-on semiconductor ATE test development experience with complex SoC/ASICs.
  • 3+ years in technical leadership or engineering management.
  • Deep knowledge of silicon bing up, DFT/DFM architectures (Scan/ATPG, MBIST, Boundary Scan, high-speed I/O testing) and OSAT production workflows.

Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

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