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IC Verification Engineer

Insight Global

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At a glance

Compensation
No compensation found
Location
San Jose, CA
Work Authorization
Not specified

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Job overview

The client seeks senior IC Verification Engineers with deep, hands‑on expertise in SystemVerilog and UVM, responsible for owning the full verification lifecycle from testbench architecture through ASIC‑cycle execution, including test planning, functional coverage, regression debugging, hardware debug, and documentation.

Skills & qualifications

RequiredNice to have

Skills

SystemVerilogUVMScalable Testbench ArchitectureVerification PlanningConstrained‑Random TestingFunctional CoverageRegression DebuggingWaveform AnalysisCoverage‑ClosureASIC Cycle ExecutionPCIe Protocol VerificationPhysical‑Layer PHY Verification

Qualifications

10+ Years ASIC, SoC, Core, or Block‑Level Design Verification Experience

Full job description

Job Description

A client of Insight Global is seeking senior IC Verification Engineers with deep, hands-on expertise in SystemVerilog and UVM. Candidates must have owned the verification lifecycle, including testbench architecture, test planning, functional coverage, regression debugging, hardware debug, and verification closure.

Responsibilities:

Architect scalable and reusable SystemVerilog/UVM testbenches

Develop verification strategies and test plans for block, core, and SoC features

Build constrained-random and pseudo-random tests

Develop functional coverage and drive verification to closure

Debug regression failures and address coverage gaps

Support hardware debug and full ASIC-cycle execution

Document verification environments, tests, and strategies

Collaborate with design and architecture teams

Skills and Requirements

10+ years of ASIC, SoC, core, or block-level design verification experience

Expert-level SystemVerilog and UVM

Experience architecting scalable, reusable UVM testbench environments

Strong verification planning, constrained-random testing, and functional coverage experience

Proven regression debugging, waveform analysis, and coverage-closure skills

Experience completing at least one full ASIC cycle from architecture through tapeout

Ability to independently lead verification for a core or major functional block

Strong teamwork, communication, coachability, and knowledge-sharing skills PCIe or another complex, multilayer protocol

Physical-layer or PHY verification experience

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].

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