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Lead Software Engineer - Low-Power Verification

Cadence Design Systems, Inc.

San Jose, CAFull-time$115–213K/yrSeen 2w agoSeen in employer's feed 3 days ago

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At a glance

Compensation
$115–213K/yr
Location
San Jose, CA
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Cadence seeks a Lead Software Engineer to develop low‑power verification software for Palladium and Protium platforms, improving UPF compilation performance, adding IEEE 1801 support, and updating documentation with example‑driven checks.

Skills & qualifications

RequiredNice to have

Skills

IEEE 1801 UPFVerilogSystemVerilogVHDLC++PerlTcl/TkPythonAI‑Assisted Coding ToolsTechnical WritingObject‑Oriented Design

Qualifications

BS in CS EE or Related FieldMS DegreePhD DegreeEquivalent Practical Experience

Benefits

Paid Time Off
401(k) Match
Medical Insurance
Dental Insurance
Vision Insurance

Full job description

SAN JOSE

Full time

R56209

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do

  • Contribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.

  • Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks.

  • Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).

  • Help consolidate and unify UPF compilation across Palladium and Protium.

What we are looking for

  • BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.

  • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).

  • Ability to read, review, and reason about C++ code and object-oriented designs.

  • Scripting experience in Perl, Tcl/Tk, and/or Python.

  • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.

  • Strong technical writing skills — able to author user guides, specifications, and workflow-first documentation.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)

Equal Employment Opportunity Policy:

Cadence is committed to equal employment opportunity throughout all levels of the organization.

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected].

Privacy Policy:

Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) .

E-Verify Cadence participates in the

E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
 Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

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