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Senior Research Scientist, Superconducting Digital Electronics, Quantum AI

Google

Washington D.C., DC · FlexibleJob$174–252K/yrSeen todaySeen in employer's feed today

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At a glance

Compensation
$174–252K/yr
Location
Washington D.C., DCFlexible
Work Authorization
Not specified

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Job overview

Google seeks a Senior Research Scientist to design and simulate superconducting digital logic circuits for quantum AI, collaborating across design, fabrication, and measurement teams to advance integrated cryogenic control electronics for large‑scale quantum computers.

Skills & qualifications

RequiredNice to have

Skills

Superconductor Logic FamiliesTape‑Out of Superconducting IC ChipsComputer‑Aided Design ToolsElectromagnetic Simulation ToolsFull Digital Design FlowLow‑Temperature MeasurementsSuperconducting Qubits

Qualifications

Master's Degree in Electrical Engineering or Physics or Related Engineering DisciplineExperience in Superconductor Logic FamiliesExperience Performing Tape-Out of a Superconducting IC ChipPublished Research Paper or Presentation at a Relevant Scientific ConferencePhD in Physics or Electrical Engineering or Related Engineering Discipline7+ Years Research/Industry Experience in Superconductor Digital Logic Design and Leading R&D GroupExperience With Full Digital Design Flow Including RTL Synthesis Verification Timing Closure Place‑and‑Route and Post‑Fabrication ValidationExperience With Low‑Temperature Measurements of Superconductor Digital Logic CircuitsExperience With Superconducting QubitsProficiency With Computer‑Aided Design Tools and Electromagnetic Simulation Tools

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k) Match
Paid Time Off
Parental Leave

Full job description

Senior Research Scientist, Superconducting Digital Electronics, Quantum AI

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corporate_fare Google place Goleta, CA, USA; Cambridge, MA, USA; +6 more; +5 more laptop_windows Remote eligible

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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The application window will be open until at least October 16, 2026. This opportunity will remain online based on business needs which may be before or after the specified date.

Applicants in San Francisco: Qualified applications with arrest or conviction records will be considered for employment in accordance with the San Francisco Fair Chance Ordinance for Employers and the California Fair Chance Act.

In accordance with Washington state law, we are highlighting our comprehensive benefits package, which is available to all eligible US based employees.

Benefits for this role include:

  • Health, dental, vision, life, disability insurance

  • Retirement Benefits: 401(k) with company match

  • Paid Time Off: 20 days of vacation per year, accruing at a rate of 6.15 hours per pay period for the first five years of employment

  • Sick Time: 40 hours/year (increased to 69 hours/year for Seattle) including 5 discretionary sick days per instance

  • Maternity Leave (Short-Term Disability + Baby Bonding): 28-30 weeks

  • Baby Bonding Leave: 18 weeks

  • Holidays: 13 paid days per year

Note: By applying to this position you will have an opportunity to share your preferred working location from the following:

In-office locations: Goleta, CA, USA; Cambridge, MA, USA; Mountain View, CA, USA; Seattle, WA, USA; San Francisco, CA, USA; Washington D.C., DC, USA.

Remote location(s): United States.

Minimum qualifications:

  • Master's degree in Electrical Engineering, Physics, related engineering discipline, or equivalent practical experience.

  • Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP).

  • Experience performing tape-out of a superconducting IC chip.

  • One or more published research paper or presentation at a relevant scientific conference.

Preferred qualifications:

  • PhD in physics, electrical engineering, or a related engineering discipline.

  • 7 years of research/industry experience in the design and simulation of superconductor digital logic circuits with 3 years of experience leading an Research and Development (R&D) group towards tape-out and demonstration of superconducting IC chips.

  • Experience with full digital design flow including RTL, synthesis, verification, timing closure, place-and-route, and post-fabrication validation.

  • Experience with low-temperature measurements of superconductor digital logic circuits.

  • Experience with superconducting qubits.

  • Proficiency with computer-aided design tools and electromagnetic simulation tools.

About the job

As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as single flux quantum (SFQ) logic and adiabatic quantum flux parametron (AQFP) logic) for qubit control and readout. You will engage in co-design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and aim performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish IC design standards that are compatible for both the sensitive superconducting qubits and the co-located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computer.

This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computers.

The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $174000 - $252000 (USD) + 15% bonus target + equity + benefits

Learn more aboutbenefits at Google (https://www.google.com/about/careers/applications/benefits/) .

Responsibilities

  • Design and simulate superconductor digital logic circuits (such as single flux quantum (SFQ) logic, adiabatic quantum flux parametron (AQFP) logic, and other emerging superconductor logic families) for generating waveforms tailored to qubit control and readout.

  • Develop superconductor digital logic systems enabling multiplexed qubit control and readout.

  • Address issues in the integration of superconductor digital electronics such as multi-layer cell design, full-chip clock synchronization, flux trapping, and signal integrity.

  • Collaborate with teams focused on design, fabrication, and measurement to validate fully integrated quantum processors.

  • Publish research papers and present at leading scientific conferences to advance and enhance publicity.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See alsoGoogle's EEO Policy (https://www.google.com/about/careers/applications/eeo/) ,Know your rights: workplace discrimination is illegal (https://careers.google.com/jobs/dist/legal/EEOC\_KnowYourRights\_10\_20.pdf) ,Belonging at Google (https://about.google/belonging/) , andHow we hire (https://careers.google.com/how-we-hire/) .

If you have a need that requires accommodation, please let us know by completing ourAccommodations for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

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