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DPU Performance Validation Engineer

NVIDIA

Yokneam, North District, IsraelFull-timePosted 1w agoStill listed 1w ago

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At a glance

Compensation
No compensation found
Location
Yokneam, North District, Israel
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

NVIDIA seeks a skilled DPU Performance Validation Engineer to characterize, debug, and validate chip architecture performance across single‑die and multi‑die systems. The role involves system‑level analysis, collaboration with design and verification teams, and development of validation methodologies within the Network Silicon Engineering group.

Skills & qualifications

RequiredNice to have

Skills

PythonC/C++LinuxRTL‑Level DebugWaveform AnalysisSystem‑Level Performance AnalysisPerformance ModelingTraffic GenerationArchitecture StudiesPCIeEthernetCHIPalladiumVeloceFPGA PrototypingSimulationEmulationValidation Methodologies DevelopmentAutomationInterpersonal Skills

Qualifications

B.Sc. In Electrical Engineering or Computer Engineering or Equivalent3+ Years Experience in ASIC Development/Validation

Full job description

We are hiring a skilled DPU Performance Validation Engineer for our DPU product lines. This includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. Working in the Network Silicon Engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future NVIDIA silicon devices. You will collaborate with Chip Design, Verification, FW, and Architecture teams to ensure successful product development with bold product cycles. The qualified candidate should be comfortable working in Simulation and Emulation environments, with strong skills in RTL-level debug, waveform analysis, and system-level performance root cause analysis.

What you will be doing:

  • Learn and analyze system-level operation of NVIDIA DPUs
  • Debug and root-cause performance issues in pre-silicon environments, across RTL, waveform traces, and multi-die system simulations.
  • Collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
  • Develop and improve validation methodologies for performance experiments and data collection.
  • Automate repetitive debug and validation tasks to scale coverage and efficiency.

What we need to see:

  • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent
  • 3+ years of experience in ASIC development/validation.
  • Strong background in ASIC debug, including reading RTL, analyzing waveforms, and root-causing functional or performance issues.
  • Hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems).
  • Proficiency with Python and C/C++ in a Linux environment.
  • Excellent interpersonal skills and ability to work optimally as part of a multi-functional team.

Ways to stand out from the crowd:

  • Shown expertise in performance modeling, traffic generation, or architecture studies.
  • Experience with modern interconnects and protocols (e.g., PCIe, Ethernet, CHI).
  • Familiarity with emulation platforms (e.g., Palladium, Veloce, FPGA prototyping).
  • Passion for experimental work, data-driven validation, and creative problem solving.

NVIDIA is widely considered to be one of the technology world’s most desirable employers with some of the most forward-thinking, inventive, and hardworking people working here – we need your help to build our future. Are you creative, high-reaching, and love challenges? We want to hear from you!

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