BITMAIN logo

物理设计工程师

BITMAIN

Beijing, Beijing, ChinaJobPosted 2w agoStill listed 3 days ago

Most applications go out cold — see where you stand first. No sign-up to start.

Watch jobs like this.

At a glance

Compensation
No compensation found
Location
Beijing, Beijing, China
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

The Physical Design Engineer will lead digital circuit physical implementation from RTL to GDS, perform full-chip STA signoff, develop and maintain design flows, and contribute to power, performance, area and yield optimization, including tool development and advanced node support.

Skills & qualifications

RequiredNice to have

Skills

SPICEEDAIntegrated Circuit DesignPythonPhysical DesignRegister Transfer LevelC3DLow-Power DesignTCLPower AnalysisInvsFcPtPxRhCalibreSta AnalysisDc SynthesisFc SynthesisPr Pi Pv PlanningEsd PlanningPpa Optimization3d Ic DesignPerlC++

Qualifications

Proven Tape-Out ExperiencePrior Experience With Sta SignoffExperience in Top-Level Pr Pi Pv PlanningFamiliarity With Signoff Standards for Advanced Process NodesExperience in Ppa OptimizationFamiliar With Low-Power Design MethodologiesFamiliar With 3d Ic Design

Full job description

Responsibility

  1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement. Requirement

  2. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes; 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage; 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred; 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++; 5. Familiar with 3D IC design; relevant experience is a plus; 6. Prior experience with STA signoff in tape-out projects is preferred.

You've read the whole posting — now see how you match it.