Senior ASIC Digital Design Engineer

Job Duties

Basic Qualifications

Education Requirements:

Requires a Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.

If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development - on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.

The right candidate has worked in larger, structured design environments where verification is a discipline in its own right - with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.

What You'll Do

• Own RTL design tasks - Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification

• Contribute to timing closure - Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes

• Support verification efforts - Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures

• Participate in JIRA triage - Review incoming issues and help maintain an accurate and actionable backlog

• Participate in code reviews - Engage in RTL code reviews, providing and receiving constructive technical feedback

• Support program planning - Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting

• Support proposals - Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks

• Support technology evaluation - Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling

• Collaborate broadly - Participate in Integrated Product Teams and working groups

What We're Looking For

• 5-8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer

• Experience working in larger, structured design teams with formal verification processes and independent verification partners - not solely in small-team or solo development environments

• Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review - not through iteration on hardware

• Some experience contributing to ASIC tape-out efforts is a plus

• Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator

• Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)

• Working knowledge of:

• RTL design and microarchitecture

• Bus fabric design and verification

• Clock domain crossing (CDC) analysis

• Reset sequencing and validation

• Timing closure fundamentals

• Power analysis basics

Skills & Knowledge

• Solid understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows

• Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)

• Ability to work independently on assigned tasks while coordinating effectively within the team

• Familiarity with vendor and foundry capabilities

• Proficiency in JIRA for issue tracking and backlog management

• Proficiency in Microsoft Office for documentation and communication

Why This Role

You won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full ASIC lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.

Target salary range: USD $142,166.00/Yr. - USD $150,000.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

General Dynamics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce. EOE/Disability/Veteran

Minimum Education Required

Bachelor Degree

Minimum Experience Required

5 - 20 years

Shift

First (Day)

Number of Openings

1

Public Transportation Accessible

Yes

Veterans Encouraged to Apply

No

Physical Required

Yes

Drug Test Required

Yes

Compensation

$142,166.00 - $150,000.00 / Annually

Postal Code

55431

Job Type

Full Time

Place of Work

On-site

Requisition ID

2026-73790

Job Benefits

Not specified