ASIC Verification Technical-Lead Engineer
Austin, TXFull-timePosted 3mo agoStill listed 3 days ago
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Job overview
Retym, Inc is hiring an ASIC Verification Technical-Lead Engineer. Retym, Inc is seeking a Verification Team-Leader to drive complex RTL design verification activities for next-generation high-speed communication technology. This role involves leading and mentoring a team of verification engineers, defining and executing verification strategies, and overseeing the development of robust verification environments. The successful candidate will collaborate with design engineers to debug issues and ensure effective resource allocation.
Key focus areas include Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables., Define and execute verification strategies and plans for complex digital blocks and systems., and Oversee the development of robust and reusable verification environments using SystemVerilog and UVM..
Successful candidates bring 10+ Years Digital Design Verification Experience, 3+ Years Managing Verification Teams, and Proven Track Record Completing Two Or More Full Block/System Verification Cycles. Important skills include Verilog, UVM, Problem-Solving, Debugging, Leadership, and Communication. Preferred (not required): Ethernet, PCIe, SerDes, and Python.
Skills & qualifications
Skills
Qualifications
Full job description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects.
Requirements:
Key Responsibilities
- Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables.
- Define and execute verification strategies and plans for complex digital blocks and systems.
- Oversee the development of robust and reusable verification environments using SystemVerilog and UVM.
- Review and approve verification plans, testbenches, and coverage metrics.
- Drive functional and coverage-based verification across multiple block/system verification cycles.
- Collaborate with design engineers to debug and resolve functionality issues.
- Ensure effective resource allocation and project planning to achieve optimal results.
- Foster a culture of technical excellence, continuous learning, and innovation within the team.
- Report verification progress, issues, and risks to senior management and other stakeholders.
Required Qualifications
- 10+ years of experience in digital design verification—a must.
- 3+ years of experience managing or leading verification teams.
- Proven track record of completing two or more full block/system verification cycles.
- In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW.
- Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM).
- Experience in block, cluster and full chip verification levels.
- Strong problem-solving skills and the ability to debug complex functionality issues.
- Excellent leadership, communication, and organizational skills to manage and inspire a team.
Preferred Qualifications
- Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes.
- Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
- Familiarity with formal verification techniques and tools.
- Background in system-level verification or post-silicon validation.
- Experience with project planning tools and methodologies for effective team management.
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