Physical Design Timing Engineer
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At a glance
Job overview
DensityAI is hiring a Physical Design Timing Engineer. The role owns full chip and block timing methodologies and execution to sign‑off of DensityAI’s AI accelerator silicon, collaborating with chip‑design and software teams to drive the AI accelerator program from first silicon through scale‑out.
Key focus areas include Own full chip and block timing methodologies and execution to‑signoff of AI accelerator silicon and Use and develop AI‑assisted tool flows to accelerate physical design timing convergence and signoff timelines.
Successful candidates bring 10+ Years Experience High Performance Designs, Experience Advanced Technology Nodes (7nm Or Better), and Experience 2.5D/3D Timing Flows. Important skills include Full Chip Timing Methodologies, Block Timing Methodologies, AI-Assisted Tool Flows, Physical Design Flow, Timing Flows, and Cadence Innovus. Preferred (not required): Post Silicon Characterization, Process Targeting, Multi-Die Packaging, and CoWoS.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
About the role Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.
What you'll do
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Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon.
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Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines.
What we're looking for
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Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies
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10+ years of experience on very high performance designs at advanced technology nodes (7nm or better) and 2.5D/3D timing flows
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Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent)
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Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips
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Post silicon characterization and process targeting experience is highly desirable
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(Optional) Multi-die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT-aware physical design
Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range $220,000 — $350,000 USD
Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
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