Senior Verification Engineer
Most applications go out cold — see where you stand first. No sign-up to start.
Don't just apply. Show up ready.
Olive works from this exact posting — no sign-up to start.
At a glance
Job overview
Retym, Inc is hiring a Senior Verification Engineer. Retym, Inc. is seeking a Senior Verification Engineer to drive complicated RTL design verification activities for next-generation high-speed communication technology. The role involves owning block/cluster verification end-to-end, leading test bench architecture efforts, and collaborating with design, architecture, and algorithm teams.
Key focus areas include Own block/cluster verification end to end from scratch., Lead efforts of test bench architecture, Vplan definition and functional coverage., and Work closely with the design, architecture, algo teams and other stakeholders..
Successful candidates bring 10+ Years Experience and At Least 2 Full Block/System Verification Cycles. Important skills include RTL Design Verification, Test Bench Architecture, Vplan Definition, Functional Coverage, VLSI Verification Flow, and eRM.
Skills & qualifications
Skills
Qualifications
Full job description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.
Requirements:
Key responsibilities:
- Ownership of block\cluster verification end to end from scratch.
- Lead efforts of test bench architecture, Vplan definition and functional coverage.
- Work closely with the design, architecture, algo teams and other stakeholders.
- Support other team members and mentor less experienced engineers.
Requirements
- 10+ years of experience – a must
- Performed at last 2 or more full block/system verification cycles.
- In depth knowledge in VLSI verification flow, languages and concepts.
- Experience in data path or data protocols, specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM, UVM, OVM).
Responsibilities
- Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
- Build verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for corner-cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrices to close the full functionality.
You've read the whole posting — now see how you match it.