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VLSI Design Engineer

Retym, Inc

Tel Aviv-Yafo, Tel Aviv District, IsraelFull-timeNo compensation foundPosted 1mo agoVerified open 4 days ago

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At a glance

Compensation
No compensation found
Location
Tel Aviv-Yafo, Tel Aviv District, Israel
Schedule
Full-time
Work Authorization
Not specified

Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Retym, Inc is hiring a VLSI Design Engineer. Retym, Inc is seeking talented and experienced VLSI Design Engineers/Micro-architects to design highly sophisticated, innovative new cutting-edge communication systems from scratch. This role involves coming up with creative solutions to architectural challenges and crafting the very fine details of implementation.

Key focus areas include Come up with creative solutions to architectural challenges and Craft the very fine details of the implementation.

Successful candidates bring Bs/Ms In Ee/Ce. Important skills include Verilog, Simulation Tools/Environments, Verification Methodologies, Team Player, Interpersonal Skills, and Entrepreneurial Can-Do Attitude. Preferred (not required): Design DSP Oriented Blocks and Ethernet 100G And Above.

Skills & qualifications

RequiredNice to have

Skills

VerilogSimulation Tools/EnvironmentsVerification MethodologiesTeam PlayerInterpersonal SkillsEntrepreneurial Can-Do AttitudeSelf-MotivatedWork IndependentlyAdvanced Design PracticesClock/Voltage Domain CrossingLow Power DesignDFTDesign DSP Oriented BlocksEthernet 100G and AbovePythonPerlTCL

Qualifications

5 Years ASIC/FPGA Designer ExperienceBS/MS in EE/CE From Lead Universities

Full job description

We are looking for talented and experienced VLIS Design Engineers/Micro-architects.

As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.

In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation

Requirements:

Job requirements:

  • 5 years of experience as ASIC/FPGA designer
  • Strong Verilog/System-Verilog experience
  • Familiar with simulation tools/environments, verification methodologies
  • Strong team player, solid interpersonal skills
  • Entrepreneurial can-do attitude, self-motivated, able to work independently
  • BS/MS in EE/CE from lead universities

Background in one or more of the following domains is an advantage:

  • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
  • Design DSP of oriented blocks
  • Ethernet (100G and above)
  • Scripting experience using several of the following: Python, Perl, TCL

You've read the whole posting — now see how you match it.