Senior Custom Design Engineer

Role Location: Zürich, Switzerland Seniority: 5+ years (custom memory or digital circuits) Design and ship high-performance, low-power SRAM and custom-digital sub-systems that sit at the core of our compute-in-memory technology. You will own architecture, circuit implementation, verification, and silicon correlation for advanced nodes, down to sub-5 nm, thereby improving both the efficiency and robustness of our macros. Expect hands-on work on memory periphery and datapath interfaces, as well as close collaboration with layout, digital, backend, DFT, and test teams. What you’ll do

• Design and verify embedded SRAM or custom digital blocks, including caches, register files, datapath, and datapath-adjacent interfaces.
• Optimize for PPA on advanced nodes: variation and stability closure, corners and Monte Carlo, leakage and dynamic power reduction.
• Integrate for product: define clean digital boundaries and timing budgets so blocks drop into a digital-on-top flow without surprises.
• Plan and run silicon correlation: bring-up, characterization benches, analysis of ATE data, clear errata, and fixes.
• Partner with layout early on floorplan, guarding, shielding, routing topology; review extraction and resolve EM/IR issues.
• Improve methods with scripts for characterization, regression, and reporting (Python or Tcl), and contribute specs, checklists, and reusable collateral.

Outcomes (first 18 months)

• Tape-in and silicon of at least one SRAM or custom-memory sub-system that meets spec across PVT, with signed correlation and test reports.
• A measurable efficiency gain on an existing macro or block you optimize, documented with before/after data.
• A reusable design and verification kit (models, plans, scripts, checklists) that shortens the following variant’s cycle time.

Requirements

• MS or PhD in Electrical or Computer Engineering and 5+ years in custom digital, analog, or SRAM design.
• Proven ownership through complete design cycleson sub-blocks.
• Strong understanding of high-performance and low-power circuit design on FinFET nodes, including bitcell stability and periphery trade-offs.
• Ability to frame and communicate clear interfaces and constraints across teams; organized, self-directed, delivery-oriented.

Nice to have

• Scripting for automation and characterization (Python, Tcl).
• Experience with memory compiler development, characterization, or verification.
• DTCO or STCO experience aligning device, bitcell, and periphery choices with product goals.
• A creative mindset and a drive for continuous improvement aimed at extreme hardware optimization.

Apply Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer) Interview flow (indicative)

• 30-min intro with HR (role/context)
• First Technical deep dive
• Second Technical Deep Dive
• (Optional) Third Technical Deep Dive
• Systems/product conversation with management