Sr. Staff Engineer, Analog/Mixed-signal IC Layout

Ayar Labs

Bengaluru, Karnataka, IndiaJobNo compensation foundPosted 3w agoVerified open 3 days ago

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At a glance

Compensation

No compensation found

Location

Bengaluru, Karnataka, India

Work Authorization

Not specified

Requirements

Credentials this posting asks for.

Associate's degree

Job overview

Ayar Labs is hiring a Sr. Staff Engineer, Analog/Mixed-signal IC Layout. Ayar Labs is seeking a Sr. Staff Engineer, Analog/Mixed-signal IC Layout to join their Silicon Engineering team in Bengaluru, India. This senior role involves the physical implementation of complex, high-performance integrated circuits, focusing on custom analog, mixed-signal, and high-speed digital blocks. The ideal candidate is an expert in advanced semiconductor process nodes, capable of driving layout methodologies and ensuring physical design meets aggressive performance, power, and area targets.

Key focus areas include Perform physical layout for critical mixed-signal components within high speed SerDes using Cadence tools, Work with AMS design engineers to optimize layout for performance and reliability, and Take part in floor planning, custom layout and verification against design rules and schematics.

Successful candidates bring Associates Degree Or Equivalent Experience, 10+ Years Analog/Mixed Signal Layout Experience, and 5+ Years FinFET Nodes Experience. Important skills include Cadence Tools, DRC/LVS Checking Flows, Calibre, Physical Layout For Critical Mixed-Signal Components, Optimize Layout For Performance And Reliability, and Floor Planning. Preferred (not required): Python, SKILL, Communication, and Integration Between Custom AMS And Digital Components In FinFET Nodes.

Skills & qualifications

RequiredNice to have

Skills

Cadence ToolsDRC/LVS Checking FlowsCalibrePhysical Layout for Critical Mixed-Signal ComponentsOptimize Layout for Performance and ReliabilityFloor PlanningCustom LayoutVerification Against Design Rules and SchematicsAdvanced Layout and Verification Methodologies for FinFET Process TechnologiesEstablish and Maintain Layout Standards, Design Rules, and Best PracticesHigh-Speed Design/Layout ConsiderationsPythonSKILLCommunicationIntegration Between Custom AMS and Digital Components in FinFET NodesLaying Out Sensitive Analog Blocks

Qualifications

Associates Degree or Equivalent Experience10+ Years Analog/Mixed Signal Layout Experience5+ Years FinFET Nodes Experience

Full job description

Position: Sr. Staff Engineer, Analog/Mixed-signal IC Layout Location: Bengaluru, India Job Id: 649 # of Openings: 0 Sr. Staff Engineer, Analog/Mixed Signal IC Layout Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an exceptionally skilled and experienced Sr. Staff IC Layout Engineer, to join our Silicon Engineering team. In this senior role, you will be responsible for the physical implementation of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate is a recognized expert in the latest advanced semiconductor process nodes, capable of driving layout methodologies and ensuring the physical design meets aggressive performance, power, and area targets

Key Responsibilities

Performing physical layout for critical mixed-signal components within high speed SerDes using Cadence tools.
Work with AMS design engineers to optimize layout for performance and reliability.
Take part in floor planning, custom layout and verification against design rules and schematics.
Define, develop, and implement advanced layout and verification methodologies for FinFET process technologies to maximize design efficiency. Establish and maintain layout standards, design rules, and best practices across the team. Basic Qualifications
Associates Degree, or equivalent experience
10+ years of hands-on analog/mixed signal layout experience, with at least 5+ years in FinFET nodes
A good understanding of high-speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
Proficient with Cadence custom layout tools
Knowledge of DRC/LVS checking flows with Calibre Preferred Qualifications
Experience with integration between custom AMS and digital components in the latest FinFET nodes.
Some knowledge of scripting languages such as Python and SKILL.
Previous experience laying out sensitive analog blocks such as PLLs, RF amplifiers, and high speed transmitters/receivers
Excellent communication skills with the ability to clearly articulate complex technical issues and solutions to cross-functional teams. NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. Apply for this Position

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