Senior Design Verification Engineer

Akeana

Location TBDFull-timePosted 1y agoStill listed 2 days ago

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At a glance

Compensation
No compensation found
Location
Location TBD
Schedule
Full-time
Work Authorization
Not specified

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Job overview

Akeana is hiring a Senior Design Verification Engineer. Senior Design Verification Engineer joins an early‑stage, well‑funded semiconductor startup, focusing on processor design, verification, and collaboration with architecture and RTL teams to deliver complex CPU and cache‑coherent subsystems.

Key focus areas include Develop unit and cluster level verification for complex CPUs, Own one or more verification areas, and Interact closely with architecture and RTL design teams.

Important skills include Design Verification, System Verilog, C++, and UVM.

Skills & qualifications

RequiredNice to have

Skills

Design VerificationSystem VerilogC++UVM

Qualifications

Strong Background in Unit/Cluster-Level VerificationProcessor Architecture ExperienceUVM ExperienceGood Knowledge of Assembly or C-Programming

Full job description

Senior Design Verification Engineer Join and be part of an exciting startup in the semiconductor space!

We are a well-funded early-stage startup doing processor design. The company was founded by industry veterans from Broadcom/Marvell/Sun Microsystems/Intel, who have taken multiple successful high-performance CPUs to tape-out and production. If you have a strong background in processors, great problem-solving skills, an eye for detail, and a can- do attitude, reach out to us, to explore opportunities.

For this position, we are looking for:

  • Strong background in unit/cluster-level verification, of a complex CPU or Cache Coherent sub- system
  • Processor architecture (such RiscV, ARM, Mips, Solaris, x86) or Cache coherency experience, and experience in previous processor verification is a plus.
  • Strong programming background in System Verilog or C++. UVM experience desirable.
  • Good knowledge of assembly or C-programming a plus You will be working with a small close-knit team and own 1 or more areas of verification. As a DV engineer you will also be interacting with Architecture, and RTL design closely. This is a great opportunity to join an early-stage startup and work on exciting designs with significant responsibility.

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