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Principal ASIC Architect

Tensordyne

Sunnyvale, CAFull-timeNo compensation foundPosted 4mo agoVerified open 6 days ago

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At a glance

Compensation
No compensation found
Location
Sunnyvale, CA
Schedule
Full-time
Work Authorization
Not specified

Requirements

Credentials this posting asks for.

Doctorate

Job overview

Tensordyne is hiring a Principal ASIC Architect. Tensordyne, a fast‑moving AI startup headquartered in Sunnyvale, CA, builds high‑performance, low‑power generative AI inference systems for data‑center workloads, leveraging novel silicon, hardware, and software to accelerate multimodal AI at scale.

Key focus areas include Lead architectural planning and definition of new AI processors, Analyze technical needs and create detailed design specifications, and Lead architectural modeling and establish ASIC development milestones.

Successful candidates bring 15+ Years Silicon Design Experience, MS Or PhD In Electrical Or Computer Engineering, and Occasional Travel Required. Important skills include ASIC Architecture Definition, High-Level Silicon Architecture Planning, ASIC Design Concepts Prototyping, Technical Leadership, Architectural Planning, and AI Processors Definition.

Skills & qualifications

RequiredNice to have

Skills

ASIC Architecture DefinitionHigh-Level Silicon Architecture PlanningASIC Design Concepts PrototypingTechnical LeadershipArchitectural PlanningAI Processors DefinitionFloating Point AI Compute CoresEmbedded MemoryEmbedded RISC-v CPU CoresHigh Speed Serial CommunicationsChip-to-Chip Networking FabricHBMPCIe ConnectivityTechnical Needs AnalysisChip Design Solutions ProposalDetailed Design Specifications CreationArchitectural ModelingASIC Development Milestones EstablishmentFunctionality RequirementsInference Performance RequirementsInference Accuracy RequirementsPower Efficiency RequirementsProgrammability RequirementsDebuggability RequirementsManufacturability RequirementsTechnical GuidanceDesign Reviews OversightCoachingSilicon IP Technologies EvaluationEDA Tools EvaluationMethodologies EvaluationSilicon Design EngineeringGPUsCPUsTPUsHigh Speed SerDes Networking Technologies for AI WorkloadsGenerative AI Algorithms UnderstandingAttention Mechanisms UnderstandingFoundation Transformer Models UnderstandingMapping Functions to HardwareVerilog ProgrammingRTL VerificationPerformance ModelingPerformance AnalysisDebuggingPerformance OptimizationArchitectural C-Models DevelopmentSystemCTLMC/C++ASIC DesignChip Design SolutionsDetailed Design SpecificationsASIC Development MilestonesDesign ReviewsEvaluation of New Silicon IP TechnologiesEDA ToolsGenerative AI AlgorithmsAttention MechanismsFoundation Transformer ModelsArchitectural C-ModelsPythonPerlAutomationSilicon Architecture PlanningAI ProcessorsFunctionalityInference PerformanceInference AccuracyPower EfficiencyProgrammabilityDebuggabilityManufacturabilityHigh Speed SerDes Networking TechnologiesAI WorkloadsVerilogRISC-VPCIeSerDesHigh Performance ComputeGPUCPUTPUASIC ArchitectureSilicon DesignHigh Speed SerDesHPC ProcessorsTransformer ModelsASIC Architecture PlanningHigh Performance Compute Processor DesignEmbedded Memory DesignHBM IntegrationGenerative AI Algorithm KnowledgeTransformer Model MappingC/C++ ProgrammingPython ScriptingHigh‑Performance Compute ProcessorsGPU ArchitectureCPU ArchitectureTPU ArchitectureHBM TechnologyHigh Speed SerDes NetworkingC++ ProgrammingPython ProgrammingPerl ProgrammingRISC-v CPU CoresC/C++ DevelopmentSystemC ModelingTLM ModelingHardware Mapping of AI FunctionsSilicon IP TechnologiesDesign MethodologiesLeadershipCross‑Functional CollaborationC Model DevelopmentMapping AI Functions to HardwareSilicon IP EvaluationC-ModelsC ModelingGPU DesignCPU DesignTPU DesignC++CChip DesignHigh Bandwidth Memory

Qualifications

15+ Years Silicon Design Engineering ExperienceMS or PhD in Electrical Engineering, Computer Engineering or Related Engineering DisciplineOccasional Travel

Full job description

About our company - Tensordyne (formerly Recogni)

AI is reshaping our world, performing cognitive tasks once unique to humans—perceiving across modalities, learning quickly, and solving complex problems. Tensordyne builds high-performance, low-power generative AI inference systems. We’re leveraging novel techniques from the latest AI research to build custom silicon, hardware, and software to accelerate multimodal generative AI at scale—delivering safe, sustainable, cutting-edge solutions for hyperscaler and neocloud data centers. Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America and Europe, Tensordyne is a well-funded, fast-moving startup. We support our people with competitive pay, comprehensive benefits, flexibility, and recognition programs—because breakthrough technology starts with a healthy, empowered team. Come join us, as we shape the future of AI together!

The Opportunity:

In this role, you will lead all phases of ASIC architecture definition and design of Tensordyne’s next-generation family of processors for generative AI inference acceleration. This is an exciting opportunity that involves high-level silicon architecture planning, hands-on design, prototyping of ASIC design concepts, mentoring, and technical leadership to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers.

  • What You'll Do:

  • Lead the architectural planning and definition of new Tensordyne AI processors, that consist of highly specialized floating point AI compute cores, embedded memory, embedded RISC-V CPU cores, and high speed serial communications with chip-to-chip networking fabric, HBM, and PCIe connectivity.

  • Analyze technical needs, propose chip design solutions, create detailed design specifications, lead architectural modeling and establish ASIC development milestones to ensure that the final product meets requirements related to functionality, inference performance, inference accuracy, power efficiency, programmability, debuggability and manufacturability.

  • Work closely with external engineering partners, ASIC design engineers, ASIC design verification teams, SOC physical design teams, interdisciplinary software teams, product management and executives, providing technical guidance, overseeing design reviews and mentoring where applicable.

  • Lead the evaluation of new silicon IP technologies, EDA tools and methodologies to enhance the product and improve the efficiency of our chip design process. What You'll Bring:

  • 15+ years of hands-on experience and deep expertise in silicon design engineering and architectural planning of high performance compute (HPC) processors like GPUs, CPUs, TPUs etc., as well as HBM and high speed SerDes networking technologies for AI workloads.

  • Strong understanding of generative AI algorithms, attention mechanisms, foundation transformer models, and mapping these functions to hardware.

  • Strong Verilog programming skills, and experience with RTL verification, and performance modeling. Experience with performance analysis, debugging, and optimization is also required.

  • Track record of developing architectural C-models, SystemC, or TLM. Expert-level skills in C/C++, and scripting languages like Python or Perl for automation and modeling.

  • An MS or PhD in Electrical Engineering, Computer Engineering or related engineering discipline. For this role, occasional travel is needed to interact with global engineering partners.

Tensordyne's culture was built on the following values:

  • Put people first. We only succeed when our people succeed.
  • Ethics and integrity always; Being open, honest, and respectful of everyone.
  • Think Big. Be ambitious and have audacious goals.
  • Aim for excellence. Quality and excellence count in everything we do.
  • Own it and get it done. Results matter!
  • Make each person better together, than they would be as an individual.
  • Embrace each others’ differences, and embrace that there will be differences.

Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

A note to Recruitment Agencies: Please don’t reach out to Tensordyne employees or leaders about our roles -- we’ve got it covered. We don’t accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.

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