Principal Timing Engineer
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Job overview
Celestial AI is hiring a Principal Timing Engineer. Marvell seeks a Principal Timing Engineer to lead post‑RTL design flow, driving synthesis, timing closure, DFT generation and ECOs for high‑speed SerDes IPs, while improving methodology and collaborating across analog and digital teams.
Key focus areas include Improve the design methodology and flow., Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data‑rates for different applications., and Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines..
Successful candidates bring Bachelor's Degree In Computer Science, Electrical Engineering Or Related Fields, 12+ Years Of Related Professional Experience, and Good Personal Communication Skills. Important skills include Synthesis, Timing Closure, DFT Generation, Timing Analysis, Physical Design, and Custom Placement And Routing. Preferred (not required): ASIC Design, ECOs, Design Methodology Improvement, and Low Power Design.
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Full job description
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